Conventional switching systems, e.g. cross point switching systems are under constant pressure to increase the number of switched inputs and outputs and their switching speed. Non-blocking cross-point switching systems, those in which any number of outputs can be connected to an input and as many as all outputs can be activated at one time are under particular pressure to improve because of the growing video/communications market. Typically the array of switching point cells is arranged in m input rows and n output rows which intersect to uniquely identify each switching cell. When a number of outputs are connected to one input, that input experiences an increasing load which slows down the response. To overcome this switch point cells are made with a buffered connection. One problem with large arrays of switching cells is that the more inputs m and outputs n there are, the larger must be the associated conductors. These conductors have associated with them resistance Rc and capacitance Cc which increase with the length of the conductors. The larger the Rc and Cc, the greater the time constant, τ, and this leads to slower response time and lower signal path bandwidth. Another source of capacitance that contributes to high τ and low bandwidth is the capacitance Cx of the switching point cells. One approach to reduce τ and increase speed and bandwidth uses a distributed bit memory, a one bit memory associated with each point cell so that instead of requiring m×n conductors to address each cell, only m+n conductors are required. The closer the point cells are together and the smaller they are, the smaller will be the area of the switching system and the shorter will be the conductors. Also, an overall smaller area produces an increased chip yield as well, since yield is inversely proportional to the area of the chip. Reducing the number of devices in each cell not only reduces their size and chip area, it also reduces the cell capacitance Cx.